The invention relates to asynchronous spread spectrum clocking.
A typical computer system uses clock signals to synchronize operations of digital circuitry of the system. Unfortunately, spectral components of these clock signals may contribute to the radiation of electromagnetic interference (EMI) emissions from the system. For example, referring to FIG. 1, the spectral components of a clock signal may include a spectral component 10 that is located at a main, or fundamental, frequency (called f.sub.0 and may be, for example, 100 MHz) as well as spectral components 12 that are located at harmonic frequencies (i.e., frequencies located at multiples of the f.sub.0 frequency).
The EMI emissions may cause undesirable interference with the circuitry of the computer system and other electronic equipment near the computer system. To reduce the EMI emissions outside of the computer system, the circuitry of the computer system may be housed inside a metal casing that prevents the EMI emissions from propagating outside of the casing. However, the casing often adds to the weight and cost of the computer system, and the casing may have a limited EMI shielding capability.
In addition to the casing, the EMI emissions may be further reduced by spread spectrum clocking (SSC), a technique that reduces the energy peaks present in the spectral components of the clock signal. In SSC, a spread spectrum clock signal (called CLK.sub.IN (see FIG. 2)) may be generated by an SSC generator 14.The SSC generator 14 typically receives a reference clock signal (from a reference clock generator 13) that has a nominal fundamental frequency (called f.sub.NOM). The SSC generator 14 modulates the reference clock signal according to a frequency-time profile 6 or 7 (see FIG. 3) to generate the CLK.sub.IN signal. Referring to FIG. 3, the CLK.sub.IN clock signal has, in place of a constant fundamental frequency, a time-varying main frequency (called f.sub.SSC) that varies slightly (varies by 1 MHz, for example) near the f.sub.NOM frequency, in a manner described below. As a result of the modulation, spectral components 18 (see FIG. 1) of the CLK.sub.IN clock signal have typically smaller magnitudes than the corresponding spectral components 10 and 12 of traditional non-SSC modulated clock signals, and as a result, the CLK.sub.IN signal typically causes fewer EMI emissions.
The frequency-time profile 6, 7 may cause the f.sub.SSC frequency to periodically vary from the f.sub.NOM frequency that is the maximum frequency to a minimum frequency that is approximately equal to (1.delta.) f.sub.NOM, where ".delta." represents an SSC modulation index. The frequency-time profile 6 may, for example, resemble a sawtooth waveform, and the frequency-time profile 7 may, for example, resemble a linear and cubic combination of the sawtooth waveform. The frequency at which the f.sub.SSC frequency cycles is often referred to as the SSC modulation frequency (called f.sub.M), and the f.sub.M frequency may be higher than audio frequencies (20 Hz to 20 kHz frequencies) but significantly lower than the f.sub.NOM frequency. As examples, the f.sub.M frequency may be near 33 kHz, and the f.sub.NOM frequency may be near 100 MHz.
Referring back to FIG. 2, the computer system may have several devices (bus devices, bridge circuits and one or more microprocessors, as examples) that synchronize operations to the CLK.sub.IN signal. To route the CLK.sub.IN signal to these devices, the computer system may include clock drivers 11 (drivers 11.sub.1, 11.sub.2 . . . 11.sub.N, as examples) that are used to fan out the CLK.sub.IN signal onto associated clock transmission lines 12 (lines 12.sub.1, 12.sub.2 . . . 12.sub.N, as examples). In this manner, a phase locked loop (PLL) 15 (PLLs 15.sub.1, 15.sub.2 . . . 15.sub.N, as examples) may be located near each device to regenerate the CLK.sub.IN clock signal from the associated clock transmission line 12. As an example, the PLL 15.sub.1 may receive and lock onto the clock signal that is finished by the transmission line 12.sub.1 to generate a clock signal (called CLK.sub.OUT1) for use by a device near the PLL 15.sub.1. The PLL 15 may be part of the device.
As an example, the CLK.sub.OUT1 clock signal ideally is a duplicate of the CLK.sub.IN signal. However, referring to FIGS. 4 and 5, the CLK.sub.OUT1 clock signal typically leads or lags the CLK.sub.IN signal by a phase error, or skew (called T.sub.S). The computer system typically is capable of tolerating some level of skew.
The clock transmission lines 12 and possibly other circuitry of the computer system that carry the clock signals may serve as antennas for EMI emissions. Unfortunately, although SSC as described above may reduce the magnitudes of the spectral components of each clock signal (and thus, reduce the amount of EMI emissions that may be attributed to that signal), by the principle of superposition, the respective spectral components of the clock signals directly sum with each other to collectively contribute to the EMI emissions. Thus, although SSC may be used, the EMI emissions may still reach unacceptable levels.
Thus, there is a continuing need for an arrangement to reduce the EMI emissions of such a system.